QUASI-HYDROPHOBIC Si-Si WAFER BONDING USING HYDROPHILIC Si SURFACES AND DISSOLUTION OF INTERFACIAL BONDING OXIDE

ABSTRACT

Methods for removing or reducing the thickness of a material layer remaining at Si-Si interfaces after silicon wafer bonding. The methods include an anneal which is performed at a temperature sufficient to dissolve oxide, yet not melt silicon.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.11/031,165, filed Jan. 7, 2005 the entire content and disclosure ofwhich is incorporated herein by reference. This application is relatedU.S. Pat. No. 7,285,473, issued on Oct. 23, 2007, and U.S. Pat. No.8,053,330, issued on Nov. 8, 2011. The '330 patent is another divisionalof U.S. patent application Ser. No. 11/031,165, filed Jan. 7, 2005.

FIELD OF THE INVENTION

The present invention generally relates to semiconductor wafer bonding,and more particularly to methods of silicon-to-silicon, i.e., Si-Si,wafer bonding in which two wafers having different Si surfaceorientations are joined and processed in such a manner as to produce abonding interface that is clean and substantially free of anyinterfacial oxide.

BACKGROUND OF THE INVENTION

Semiconductor device technology is increasingly relying on specialtySi-based substrates to improve the performance of complementary metaloxide semiconductor (CMOS) devices, such as nFETs (i.e., n-channelMOSFETs) or pFETs (i.e., p-channel MOSFETs). For example, the strongdependence of carrier mobility on silicon orientation has led toincreased interest in hybrid orientation Si substrates in which nFETsare formed in (100)-oriented Si (the orientation in which electronmobility is higher) and pFETs are formed in (110)-oriented Si (theorientation in which hole mobility is higher), as described, forexample, by M. Yang, et al. “High Performance CMOS Fabricated on HybridSubstrate with Different Crystal Orientations,” IEDM 2003 Paper 18.7 andU.S. patent application Ser. No. 10/250,241, filed Jun. 17, 2003entitled “High-performance CMOS SOI devices on hybrid crystal-orientedsubstrates”, now U.S. Pat. No. 7,329,923.

While there are a variety of approaches for fabricating hybridorientation substrates, all share a fundamental requirement for sometype of bonding and layer transfer to produce regions of semiconductorwith a first orientation (derived from a first semiconductor wafer) andregions of semiconductor with a second orientation (derived from asecond semiconductor wafer).

Most Si wafer bonding techniques utilize hydrophilic bonding, in whichan oxide (or native oxide) is disposed on both of the wafer surfaces tobe bonded. Hydrophilic bonding is a suitable approach when an oxide isdesired at the bonded interface (for example, when fabricatingsilicon-on-insulator (SOI) substrates). However, some applicationsrequire direct Si-to-Si bonding, with no oxide layer at the bondedinterface. For example, fabrication of hybrid orientation substrates byamorphization/templated recrystallization (ATR) methods such asdescribed, for example, by U.S. patent application Ser. No. 10/725,850,filed Dec. 2, 2003 entitled “Planar substrate with selectedsemiconductor crystal orientations formed by localized amorphization andrecrystallization of stacked template layers”, now U.S. Publication No.2005/0116290, requires a clean Si/Si interface between Si surfaceshaving different surface orientations (e.g., (110) Si and (100) Si).

Such direct Si-to-Si bonding is normally achieved with hydrophobicbonding, a more difficult and less well developed technique than themore commonly used hydrophilic bonding. Hydrophobic bonding is arelatively difficult technique for several reasons. Hydrophobic(H-terminated) surfaces are more easily contaminated than hydrophilicones, often leading to a choice to perform hydrophobic bonding in avacuum environment. In addition, the widely used surface plasmatreatments developed to allow room temperature bonding typicallyintroduce surface oxygen, making them incompatible with an oxide-freebonded interface. Bonding at higher temperatures also can presentdifficulties, since most cleaving processes (used to separate the bondedlayer from the wafer to which it was originally attached) are thermallyactivated and start occurring in the same temperature range as thebonding.

Direct Si-to-Si wafer bonding could be greatly simplified if one had a“quasi-hydrophobic” bonding method in which an ultrathin (1-2 nm) oxidewould be present on one or both wafer surfaces during bonding (allowingthe bonding to be hydrophilic), but made to disappear by removing itafter the bonding to leave the desired direct Si-to-Si contact at thebonded interface.

The dissolution and/or islanding of buried oxide layers between bondedSi wafers has been examined previously as a function of Si wafer doping,Si wafer growth (float-zone (FZ) or Czochralski (Cz)), and Si wafersurface orientation. Both P. McCann, et al. “An investigation intointerfacial oxide in direct silicon bonding,” 6th Int. Symp. onSemiconductor Wafer Bonding, San Francisco, Sep. 2-7, 2001, and K.-Y.Ahn, et al. “Stability of interfacial oxide layers during silicon waferbonding,” J. Appl. Phys. 65 561 (1989) utilized N₂ annealing attemperatures in the range from 1100°-4200° C. It was concluded thatdissolution of native oxides having a thickness greater than 1 nm is notpossible, and that undesirable oxide islanding is typical, especiallywith Cz wafers.

An example of this islanding is shown schematically in FIGS. 1A-1B. FIG.1A shows a cross section view of a bonded structure 10 before an annealthat produces islanding. Bonded structure 10 in FIG. 1A comprises asubstrate silicon wafer 20, a bonded silicon layer 30, and a continuousoxide layer 40 at an interface 50. After annealing, the oxide layer 40breaks up into islands 60, as shown in FIG. 1B.

In contrast to these results, it was shown that a few monolayers ofinterfacial oxide could be made to disappear in FZ wafers afterannealing at 1150° C. Unfortunately, FZ wafers are still very expensive,are relatively easily deformed during processing, and typically are usedonly in cases where high resistivity substrates are required. Moreover,it is expected that interfacial oxide layers will never be as thin as afew monolayers, if the bonding is done in any environment other thanhigh vacuum.

In view of the above, it would be desirable to have a method forremoving the ultrathin interfacial oxide remaining at the Si-Siinterface after bonding. More particularly, it would be desirable tohave a method for removing ultrathin interfacial oxides remaining afterhydrophilic Si-Si wafer bonding to create bonded Si-Si interfaces havingproperties comparable to those achieved with hydrophobic bonding.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a method for removingan ultrathin interfacial oxide (on the order from about 0.5 to about 4nm) remaining after hydrophilic Si-Si wafer bonding, thereby allowingformation of a Si-Si interface comparable to those achieved withhydrophobic bonding with the convenience of hydrophilic bonding.

Another object of the present invention is to provide a method forthinning or removing undesired material disposed at a bonded interfacebetween two silicon-containing semiconductor materials.

A further object of the present invention is to provide a method forforming a Si layer-to-Si wafer bonded wafer couple in which the Si-to-Siinterface is both oxide-free and formed by hydrophilic bonding.

The first-mentioned object of the present invention is achieved by anoxide dissolution process in which a bonded Si-Si interface including anultrathin oxide layer is annealed at an elevated temperature (e.g., fromabout 1200° to about 1400° C.) in an ambient for a time long enough todissolve the oxide (e.g., 1 min to about 24 hours). Specifically, abonded structure comprising a first Si material and a second Si materialseparated by an ultrathin oxide layer is provided and then the bondedstructure is annealed at a temperature sufficient to dissolve oxide, yetnot melt the Si materials.

The ultrathin oxide layer at the bonded Si-Si interface would typicallyhave an initial thickness of about 2 to about 3 nm. The oxide layermight comprise (or be derived from) a native silicon oxide, a chemicaloxide (e.g., as produced by a wet chemical clean), a thermally grownoxide, an oxide deposited by chemical vapor deposition, or an oxideformed as the result of a plasma treatment.

Regarding the more general object of this invention, a similar annealingprocess may be used to thin or remove undesired material disposed at abonded interface between two silicon-containing semiconductor materials.For example, the similar annealing process might be used to remove anO-containing material from the interface between two SiGe layers.

Regarding the final object of the present invention, a method isprovided to form a bonded Si layer-to-Si wafer couple in which theSi-to-Si interface is oxide-free yet formed by bonding of hydrophilic Sisurfaces. The steps of the this embodiment of the present inventioninclude:

selecting a handle wafer with a Si surface to be bonded;

selecting a donor wafer with a Si surface to be bonded, the donor waferpreferably including a cleave plane or etch-stop region at somepredetermined depth from the donor wafer surface;

subjecting the bonding surfaces of the two wafers to cleaning andsurface treatments known to the art, leaving the bonding surfaceshydrophilic without introducing more than about 3 to about 5 nm of oxideon either bonding surface;

bonding the wafers by methods known to the art;

removing undesired portions of the donor wafer to leave a transferreddonor wafer layer;

performing surface treatments on the transferred donor wafer layer, asnecessary, to leave the bonded donor wafer layer with the desiredsurface finish and thickness; and

performing the novel oxide dissolution process of this invention toremove the interfacial material remaining at the bonded interface.

It should be noted that the aspect of the present invention relating toSi-to-Si bonding is used to best advantage when the Si surfaces at thebonded interface have different surface orientations, for example, whena Si surface having a (100) orientation is bonded to a Si surface havinga (110) orientation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1B are pictorial representations (through cross sectionalviews) illustrating a bonded silicon-to-silicon interface before (FIG.1A) and after (FIG. 1B) a prior art attempt to remove an interfacialoxide layer.

FIGS. 2A-2B are pictorial representations (through cross sectionalviews) illustrating the various processing steps of the inventive oxidedissolution process for removing or reducing the thickness of aninterfacial oxide between two bonded silicon surfaces.

FIGS. 3A-3B are pictorial representations (through cross sectionalviews) illustrating the various processing steps of the inventive oxidedissolution process for the case in which one of the bonded siliconsurfaces is disposed on a buried oxide layer.

FIGS. 4A-4E are pictorial representations (through cross sectionalviews) illustrating how the oxide dissolution process of the presentinvention may be incorporated into a hydrophilic Si-to-Si bonding methodto produce a wafer structure with bonded Si-Si interfaces havingproperties comparable to those achieved with hydrophobic bonding.

FIGS. 5A-5C are pictorial representations (through cross sectionalviews) illustrating intermediate steps of the inventive oxidedissolution process for the case in which the interfacial oxide isremoved in a mildly oxidizing annealing ambient in the absence of aprotective cap layer.

FIGS. 6A-6D are pictorial representations (through cross sectionalviews) illustrating intermediate steps of the inventive oxidedissolution process for the case in which the interfacial oxide isremoved in an inert or mildly oxidizing annealing ambient afterdeposition of a protective cap layer.

FIGS. 7A-7B show cross section view transmission electron micrographs(TEMs) of a bonded interface before (FIG. 7A) and after (FIG. 7B) theannealing treatment of the present invention.

FIG. 8A-8B show reflectance vs. wavelength data for the samples of FIGS.7A-7B.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described in more detail by referringto the drawings that accompany the present application. In theaccompanying drawings, like and corresponding elements are referred toby like reference numerals. It is also noted that the drawings of thepresent invention representing the structures during the variousprocessing steps of the present invention are provided for illustrativepurposes and are thus not drawn to scale.

Reference is first made to FIGS. 2A-2B which show a cross sectionschematic view of the initial and final steps of the inventive oxidedissolution process for removing or reducing the thickness of aninterfacial oxide between two bonded silicon surfaces for the case wherethe two silicon surfaces have different surface orientations. Thedifference surface orientations can include, for example, any major orminor axis of a Si wafer. FIG. 2A shows a starting structure 100comprising Si layer or handle wafer 110 having a first orientation, asilicon-on-insulator (SOI) layer 120 having a second orientationdifferent from the first orientation, and an ultrathin buried oxide(box) layer 130 separating elements 110 and 120. Ultrathin oxide layer130 would typically be less than 5 nm thick. Starting structure 100 isthen exposed to the oxide dissolution process of this invention toproduce structure 150 of FIG. 2B with oxide-free interface 140, andfinal Si layer 120′, which may in some cases be thinner than the initialSi layer 120.

FIGS. 3A-3B show the initial and final steps of the inventive oxidedissolution process for the case in which one of the bonded siliconsurfaces is disposed on a moderately thick buried oxide or otherinsulating layer 180 on handle wafer 111. Structures 160 and 170 ofFIGS. 3A and 3B are analogous to structures 100 and 150 of FIGS. 2A and2B. As described in Ser. No. 10/725,850, structures such as 170 of FIG.3B can be useful as a starting substrate for fabricating SOI hybridorientation substrates by certain ATR methods. Buried oxide layer 180typically has a thickness from about 100 to about 200 nm. The inventiveoxide dissolution process will cause some thinning of layer 180, but itis less consequential (because thickness changes of around 3 nm are asmall fraction of buried oxide layer 180's initial thickness).

The different surface orientations of silicon layer or handle wafer 110and SOI layer 120 may be selected from (100), (110), (111), and thelike.

FIGS. 4A-4E show how the oxide dissolution annealing process of thepresent invention can be incorporated into a hydrophilic Si-to-Sibonding method to produce a wafer structure with bonded Si-Si interfaceshaving properties comparable to those achieved with hydrophobic bonding.FIG. 4A shows a handle wafer 112 with a Si bonding surface 113, and adonor wafer 114 with a Si bonding surface 115 and an optional cleaveplane or etch-stop region 116. FIG. 4B shows the wafers of FIG. 4A aftercleaning and surface treatments which leave the bonding surfaceshydrophilic and with surface oxide layers 117 that are less than about 3to about 5 nm thick. FIG. 4C shows the wafers of FIG. 4B after bonding.A bonded wafer couple 118 with combined interfacial oxide layer 182 isthen produced by using bonding methods known to the art (see forexample, Q.-Y. Tong and U. Gosele, Semiconductor Wafer Bonding Scienceand Technology, John Wiley (New York, 1999), or U.S. patent applicationSer. No. 10/696,634, now U.S. Pat. No. 7,023,055; the entire content ofeach is incorporated herein by reference). FIG. 4D shows the structureof FIG. 4C after undesired portions of the donor wafer have been removedto leave a structure 184 with a transferred donor wafer layer 186. Theoxide dissolution process of the present invention is then used toremove interfacial material remaining at the bonded interface to producethe structure of FIG. 4E with an oxide-free interface 188.

It should be noted that handle and donor wafers 112 and 114 may includesubsurface insulating or semiconductor layers or other structures notshown in FIG. 4A. It should also be noted that the transferred donorwafer layer 186 may be subjected to surface treatments as necessary toleave the layer with the desired surface finish and thickness, and thatvarious anneals may be performed after bonding to improve bond strength.

FIGS. 5 and 6 show the intermediate steps of the oxide dissolutionannealing process used in FIGS. 2-4. FIG. 5 is for the case in which theoxide dissolution anneal is performed in a mildly oxidizing annealingambient without a protective cap layer, and FIG. 6 is for the case inwhich the oxide dissolution anneal is performed in an inert annealingambient after deposition of a protective cap layer.

In both cases, the oxide dissolution anneal of the invention ispreferably performed at a temperature in the range from about 1200° toabout 1400° C., in an ambient for a time duration in the range fromabout 1 min to about 24 hours. More preferably, the anneal is performedat a temperature in the range from about 1300° to about 1330° C., in anatmospheric-pressure ambient for a time duration of about 1 to about 5hours. Ramp rates are preferably in the range from about 0.1 to about10° C./min, with ramp rates at the lower end of this range preferred fortemperatures above 1200° C.

FIGS. 5A-5C illustrate the inventive oxide dissolution annealing processfor the case of no protective cap layer. FIG. 5A shows the startingstructure 100 of FIG. 2A before annealing. FIG. 5B shows structure 100of FIG. 5A after annealing in a mildly oxidizing ambient in theabove-described preferred time/temperature range to produce structure190 with an oxide-free interface 140, a thinned Si layer 120′, and areaction layer 200 resulting from reactions of the Si layer 120 withoxygen or other reactive species in the annealing ambient. Reactionlayer 200, typically comprising SiO₂, may then be removed by any processknown to the art (e.g., wet etching in an HF-containing solution) toform structure 150 of FIGS. 2B and 5C.

Trace amounts of O₂ are typically deliberately incorporated into theannealing ambient to prevent pitting of exposed Si surfaces. Too low anoxygen concentration will lead to Si roughening and pitting via theformation and desorption of volatile Si suboxides (e.g., SiO). Too highan oxygen concentration in the ambient will lead to the formation of athick surface SiO₂ layer and substantial Si consumption. Addition ofoxygen in the range from about 0.02 to about 2% O₂ allows the formationof a uniform, very slowly growing SiO₂ layer which keeps the Si surfacerelatively smooth.

Protective cap layers may be used to minimize or eliminate siliconconsumption during the annealing process of the present invention, asshown in FIGS. 6A-6D. FIG. 6A shows the starting structure 100 of FIG.2A before annealing. FIG. 6B shows structure 100 of FIG. 6A afterdeposition of protective cap layer 210. The structure of FIG. 6B is thenannealed in an inert or mildly oxidizing ambient in the above-describedpreferred time/temperature range to dissolve away the ultrathin oxidelayer 130, producing the structure of FIG. 6C, with an oxide-freeinterface 140, a negligibly thinned Si layer 120″, and possibly anat-least-partially-oxidized protective cap layer 210′. Cap layer 210′ isthen removed after the anneal to produce the structure of FIG. 6D.

Protective cap layer 210 would typically comprise one or more layers ofdeposited materials that are thermally stable, non-reactive with respectto the underlying semiconductor regions, and easy to selectively removeafter the anneal. Preferred materials for a deposited protective caplayer include one or more layers selected from the group of materialsincluding SiO₂, SiN_(x), or SiO_(x)N_(y), Si (amorphous, polycrystallineor single crystalline). Protective cap layer thicknesses are preferablyin the range from about 30 to about 500 nm.

The need for an oxidizing ambient for the high temperature annealingstep is lessened with the use of a protective cap layer. As mentionedabove, some O₂ is normally deliberately added to the annealing ambient,to tilt the SiO₂(s)—SiO(s)—SiO(g) equilibrium towards SiO₂(s) formationand away from SiO(g) desorption (which can lead to etching and pittingof the Si surface). Both SiO₂ and SiN_(x) cap layers protect the Sisurface by interfering with the adsorption of oxygen and the desorptionof any SiO resulting from the substrate Si oxidation. However, SiN_(x)cap layers are potentially less volatile than SiO₂, since SiO₂ can reactwith oxygen-containing species in the ambient to form SiO(g) and (ifH-containing gases are present in the ambient) other volatile speciessuch as SiO_(x)H_(y). But SiN_(x) layers are vulnerable to at least somesurface oxidation, and formation of some SiO_(x)N_(y) is expected evenin ambients without deliberately added O₂.

Several preferred protective cap layers will be described below, alongwith their advantages and disadvantages:

(A) Substrate/SiO₂. A preferred protective cap layer might comprise athick (on the order of about 50 to about 500 nm) layer of SiO₂. Such acap layer has the advantage of being simple and effective. However,SiN_(x) layers can be better diffusion barriers to oxygen, and, asmentioned above, oxide caps are still susceptible to thinning.

(B) Substrate/SiO₂/SiN. A preferred bilayer protective cap mightcomprise a thin (on the order of about 5 to about 20 nm) bottom layer ofSiO₂ in combination with a thicker (on the order of about 50 to about200 nm) SiN_(x) overlayer. After the anneal, surface SiO_(x)N_(y) formedby oxidation of the SiN_(x) overlayer can be removed by etching indilute HF, and the remaining SiN_(x) overlayer can be easily selectivelyetched with respect to the underlying SiO₂ in hot phosphoric acid.However, high annealing temperatures can lead to undesired mixing of theoxide underlayer with the nitride overlayer to form the oxynitrideSi₂N₂O (or one of similar composition), which is insoluble in both HFand hot phosphoric acid. This problem can be overcome by etching inHF-ethylene glycol solutions which has roughly equal rates for nitrides,oxides and oxynitrides. In contrast to the Si₂N₂O oxynitride, thesurface SiO_(x)N_(y) formed by reaction of SiN_(x) with O₂ is readilyremoved in dilute HF at roughly the rate of a thermal SiO₂ oxide

(C) Substrate/SiO₂/Si. A preferred bilayer protective cap might comprisea thin bottom layer of SiO₂ in combination with a thicker overlayer ofpolycrystalline or amorphous silicon. The uppermost portion of thedeposited Si is converted to an oxide layer during the anneal. Thisoxide is removed by HF, the Si can be removed by any number of etchesthat are selective to oxide, e.g., tetra-methyl ammonium hydroxide(TMAH), various reactive ion and/or plasma processes, etc. The remainingthin SiO₂ layer on the substrate may then removed by HF. Thicknesses forthe bottom layer need to be significantly higher than about 5 to about10 nm in order to allow for the expected thickness reduction resultingfrom oxide dissolution into the overlying polycrystalline Si. Preferredlayer thicknesses might be from about 20 to about 50 nm for the thinSiO₂, and about 100 to about 200 nm for the poly-Si overlayer.

(D) Substrate/SiO₂/Si/SiO₂. A preferred protective cap might comprise athin (on the order from about 20 to about 50 nm) bottom layer of SiO₂ incombination with a thicker (on the order from about 50 to about 100 nm)overlayer of polycrystalline or amorphous silicon, followed by a toplayer of SiO₂. The top layer of SiO₂ reduces the required thickness ofSi as well as the amount of silicon oxidation. As with the SiO₂/Siprotective cap described above in (C), it is best not to make the bottomSiO₂ layer too thin.

In general, the annealing ambient may comprise vacuum or at least onegas selected from the group including Ar, He, Kr, Ne, Xe, N₂, O₂, H₂,H-containing gases, C-containing gases, F-containing gases,Cl-containing gases, Si-containing gases, halogen-containing gases,O-containing gases, and mixtures thereof.

The ultrathin oxide layer at the bonded Si-Si interface would typicallyhave a thickness of about 0.5 to about 4 nm, with thicknesses in therange of about 2 to about 3 nm being more typical. The oxide layer mightcomprise (or be derived from) a native silicon oxide, a chemical oxide(e.g., as produced by a wet chemical clean), a thermally grown oxide, anoxide deposited by chemical vapor deposition, or an oxide formed as theresult of a plasma treatment. The oxide layer may further include otherelements in addition to silicon and oxygen, such as, for example, one ormore elements comprising C, Cl, F, Ge, H, N, S, As, B, P, Sb or Sn.

A more general aspect of this invention pertains to using theabove-described high temperature annealing to remove or reduce thethickness of undesired material disposed at a bonded interface of twosilicon-containing semiconductor materials. The undesired material maycomprise a layer containing at least one element comprising C, Ge, N, Oor Si, for example, a silicon oxide, nitride or oxynitride. The twosilicon-containing semiconductor materials may be the same or differentin surface crystal orientation, microstructure (single-crystal,polycrystalline, or amorphous), and composition. SiGe alloys are oneexample of Si-containing semiconductor materials falling within thescope of this invention; others include SiC and SiGeC, as well as any ofthe aforementioned Si-containing materials including at least onedopant.

The inventive method is used to best advantage when the Si surfaces atthe bonded interface have different surface orientations, for example,when a Si surface having a (100) orientation is bonded to a Si surfacehaving a (110) orientation. In a more general aspect of the invention,the similar annealing processes may be used to remove undesired materialdisposed at a bonded interface of two silicon-containing semiconductormaterials. The two silicon-containing semiconductor materials may be thesame or different in surface crystal orientation, microstructure(single-crystal, polycrystalline, or amorphous), and composition.

The following example is provided to illustrate the present inventionand to demonstrate the efficacy of the same.

EXAMPLE

This example illustrates how the method of the present invention wasused to remove an interfacial oxide present at the bonded interfacebetween a (100)-oriented Si layer and a (110)-oriented Si handle wafer.Interfacial oxide removal was established by comparing transmissionelectron micrograph (TEM) images (FIG. 7) and optical reflectance data(FIG. 8) before and after annealing.

FIG. 7A shows a TEM image of a substrate structure 300 analogous to 100of FIG. 2A or 5A, with (110)-oriented Si handle wafer 320,(100)-oriented Si layer 310 having a thickness of 160 nm, andinterfacial oxide layer 330 having a thickness of 2-3 nm remaining aftera 2 hour bonding anneal at 1000° C. The gray-scale color contrastbetween Si layer 310 and Si handle wafer 320 results from the differencein their crystal orientations.

The solid trace in FIG. 8A shows reflectance vs. wavelength data for thesubstrate structure 300. The oscillations in the wavelength range400-800 nm (absent from the dotted trace of FIG. 8B for a bulk(100)-oriented Si wafer) indicated the presence of a buried oxide layer.

Substrate structure 300 was then subjected to an anneal comprising thefollowing steps:

250°-950° C., 5° C./min, Ar+1.2% O₂

950°-4200° C., 3° C./min, Ar+0.13% O₂

1200°-4325° C., 1° C./min, Ar+0.063% O₂

1325° C./5 h, Ar+0.063% O₂

1325°-4200° C., −3° C./min, Ar+0% O₂

1200°-400° C., −5° C./min, N₂

The anneal produced about 80 nm of surface oxide, corresponding to asilicon consumption of about 36 nm.

FIG. 7B shows a TEM image of substrate structure 300 after annealing andsurface oxide removal by aqueous HF produces substrate structure 340.Interfacial oxide 330 was gone, leaving an array of planar stackingfaults 350 at the interface between differently oriented silicon regions310′ and 320. Surface Si layer 310′ was slightly thinner than originallayer 310, and handle wafer 320 remained the same.

The solid trace of FIG. 8B shows reflectance vs. wavelength data forsubstrate structure 340. Oscillations in the wavelength range 400-800 nmwere nearly absent, and the trace was nearly identical to the dottedtrace for a bulk (100)-oriented Si wafer. While less definitive than theTEM data of FIG. 7B, this was at least suggestive of a very substantialreduction in interfacial oxide thickness. It should be noted that thethickness difference between layers 310 and 310′ was not enough toaccount for the decreased oscillation amplitude, since strongoscillations were still present in the dotted trace of FIG. 8A for asample formed from substrate 300 by simply thinning layer 310 to thethickness of layer 310′ (without affecting interfacial oxide 330).

While the present invention has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the spirit and scope ofthe present invention. It is therefore intended that the presentinvention not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

1. A method for reducing the thickness of a material layer comprising atleast one of C, Ge, N, O or Si between two bonded silicon surfacescomprising annealing a structure including said material layercomprising at least one of C, Ge, N, O or Si between said two bondedsilicon surfaces at a temperature sufficient to dissolve oxide, yet notmelt silicon.
 2. The method of claim 1 wherein said two bonded siliconsurfaces comprise a first silicon surface with a first single crystalsurface orientation and a second silicon surface with a second singlecrystal surface orientation, said second single crystal surfaceorientation is different from said first single crystal surfaceorientation.
 3. The method of claim 1 wherein said temperature is fromabout 1200° to about 1400° C.
 4. The method of claim 3 wherein saidannealing is performed at said temperature for a time period from about0.1 to about 24 hours.
 5. The method of claim 1 wherein said annealingis performed in an ambient comprises at least one gas selected from thegroup consisting of Ar, He, Kr, Ne, Xe, N₂, O₂, H₂, H-containing gases,C-containing gases, F-containing gases, Cl-containing gases,Si-containing gases, halogen-containing gases, O-containing gases, andmixtures thereof.
 6. The method of claim 5 wherein said ambient isoxidizing.
 7. The method of claim 1 further comprising depositing adisposable protective cap layer before said annealing and removing saiddisposable protective cap layer after said annealing.
 8. The method ofclaim 1 further comprising removing any surface oxide layer producedduring said annealing by wet etching.
 9. A method for reducing thethickness of an interfacial oxide between a bonded silicon surface and asilicon-containing semiconductor surface comprising annealing astructure including said interfacial oxide between said two bondedsurfaces at a temperature sufficient to dissolve oxide, yet not meltsilicon.
 10. The method of claim 9 wherein said two bonded siliconsurfaces comprise a first silicon surface with a first single crystalsurface orientation and a second silicon surface with a second singlecrystal surface orientation, said second single crystal surfaceorientation is different from said first single crystal surfaceorientation.
 11. The method of claim 9 wherein said temperature is fromabout 1200° to about 1400° C.
 12. The method of claim 11 wherein saidannealing is performed at said temperature for a time period from about0.1 to about 24 hours.
 13. The method of claim 9 wherein said annealingis performed in an ambient comprising at least one gas selected from thegroup consisting of Ar, He, Kr, Ne, Xe, N₂, O₂, H₂, H-containing gases,C-containing gases, F-containing gases, Cl-containing gases,Si-containing gases, halogen-containing gases, O-containing gases, andmixtures thereof.
 14. The method of claim 9 wherein said annealing isperformed in an oxidizing ambient.
 15. The method of claim 9 furthercomprising depositing a disposable protective cap layer before saidannealing and removing said disposable protective cap layer after saidannealing.
 16. The method of claim 9 further comprising removing anysurface oxide layer produced during said annealing utilizing a wetetching.
 17. A method of fabricating a semiconductor structurecomprising: annealing a bonded structure including an interfacial oxidebetween two bonded silicon surfaces in an ambient that is selected fromthe group consisting of O₂, H₂, H-containing gases, C-containing gases,F-containing gases, Cl-containing gases, Si-containing gases,halogen-containing gases, O-containing gases, and mixtures thereof, andat a temperature sufficient to dissolve oxide, yet not melt silicon. 18.The method of claim 17 wherein said two bonded silicon surfaces comprisea first silicon surface with a first single crystal surface orientationand a second silicon surface with a second single crystal surfaceorientation, said second single crystal surface orientation is differentfrom said first single crystal surface orientation.
 19. The method ofclaim 17 wherein said temperature is from about 1200° to about 1400° C.20. The method of claim 17 wherein said annealing is performed at saidtemperature for a time period from about 0.1 to about 24 hours.